CSMC provides in-house design, ARM 7-track Library and Verisilicon 9-track Library on both 0.13μm and 0.18μm process, which include standard cell, I/O and memory compilers.
In addition, CSMC also provides 0.5μm/0.35μm Mixed-signal, 0.5μm Bipolar-CMOS-DMOS and 0.5μm High voltage process standard cell and I/O cell Library, 0.18μm Mixed-Signal, HV BCD, NVM, MCU and 0.153μm Enhance CMOS process standard cellLibrary, with different routing pitches to help customers to achieve optimal die sizes and effective cost. These Libraries offer robust ESD protection. All of them support Cadence and Synopsys ASIC SOC design flow.
All these Libraries offer customers a choice of Library implementation options. CSMC facilitates the relationship between customers and Library vendors to ensure successful tape-out, and faster time-to-market.
Libraries
| Tech.Node | Library Type | Available Libraries |
|---|---|---|
| 0.11μm Eflash | 6T Library | 6 Track Standard Cell Library, PMK, Inline I/O, Stagger I/O, Memory Compiler |
| 0.13μm G | 7 Track Metro Library | 7 Track Standard Cell Library, PMK, Inline I/O, Stagger I/O, Memory Compiler |
| 9 Track Library | 9 Track Standard Cell Library, Inline I/O, Stagger I/O, Memory Compiler | |
| 0.153μm CMOS EN | 7 Track & 9 Track Library | 7 Track & 9 Track Standard Cell Library |
| 0.18μm G | 7 Track & 9 Track Library | 7 Track & 9 Track Standard Cell Library, Inline I/O, Stagger I/O, DUP I/O,RF I/O, Memory Compiler |
| 0.18μm CMOS EN | 9 Track & 11 Track&13 Track Library | 9 Track & 11 Track &13 Track Standard Cell Library, Memory Compiler |
| 0.18μm BCD | 9 Track & 13 Track Library | 9 Track & 13 Track Standard Cell Library, Memory Compiler |
| 0.25μm BCD | 12 Track Library | 12 Track Standard Cell Library |
| 0.35μm Mix | 9 Track Library | 9 Track Standard Cell Library, Inline I/O, Stagger I/O, Memory Compiler |
| 0.35μm Logic | 9 Track Library | 9 Track Standard Cell Library |
| 0.5μm MS | 9 Track Library | 9 Track Standard Cell Library, Inline I/O |
| 0.5μm BCD | 9 Track Library | 9 Track Standard Cell Library, Inline I/O |
PDKs
| Tech.Node | Available PDKs Based On Cadence Design Tools |
|---|---|
| 0.5μm | Mixed-Signal,Mixed-Signal High Cap.;BCD;High Voltage;0.5μm FE 0.35μm BE;0.5μm FE 0.35μm BE High Cap. |
| 0.35μm | Mixed-Signal |
| 0.25μm | MS/BCD |
| 0.18μm | Mixed-Signal/RF/High Voltage/FLASH/EEPROM/BCD/CMOS EN |
| 0.153μm | CMOS EN |
| 0.13μm | Mixed-Signal/RF |
| 0.11μm | ULL/Eflash |
| Tech.Node | Available PDKs Based On Empyrean Design Tools-Aether |
|---|---|
| 0.5μm | Mixed-Signal |
| 0.35μm | Mixed-Signal |
